Sr. Timing Clocking Convergence Engineer - 710204
Intel - Santa Clara, CA

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Sr. Timing Clocking Convergence Engineer - 710204 Description If you're interested in products going into future super computer markets then the Intel® Many Integrated Core (Intel® MIC) Hardware Engineering Group is the place for you! We design and validate silicon chips with many Intel cores integrated inside for use in high performance computing architectures.

We are looking for a design engineer experienced in timing and clocking to join a senior Intel® MIC integration/convergence team. The charter of the sub-team is to drive the development and deployment of the project timing and clocking methodology, hierarchical rollup, and work models and to facilitate and shepherd timing and clocking convergence of Intel® MIC HPC complex hierarchical designs.

In this position, your responsibilities will include but not be limited to:
- Interpretation of performance requirements and translation into concrete timing/clocking specifications
- Participating in the advancement of timing convergence technology and work model
- Facilitating timing convergence of cutting-edge HPC microprocessors
- Researching features of design and static timing analysis tools, and formulating the full scope of timing and clocking methodology for next generation processor designs to improve efficiency and accuracy
- Design reviews and audits to ensure landing zone convergence requirements are met project-wide
- Participation in post-Si timing debug and correlation

You should have strong communication, organization, and teamwork skills. You should also have the capability of managing a high-intensity, dynamic work environment.


Minimum Qualifications:
Candidate must have a Bachelor's degree with 6 years' experience or a Master's degree with 4 years' experience. Degree should be in Electrical Engineering and/or Computer Science, or related field. Experience should be in the following areas:
- Experience with tight technical team interactions for technological advancement and facilitation of stringent timing/clocking convergence goals
- Strong familiarity with processor design and convergence
- Strong familiarity with static timing analysis and clocking concepts
- Familiarity with clock distribution theory, approaches, issues

Preferred Qualifications:
- Familiarity with PrimeTime
- Strong software skills (Perl and/or C and/or C++ and/or Tcl/Tk)
- Excellent interpersonal skills for interaction with internal and external tool vendors
- Good customer support skills spanning multiple design sites
Job Category : Engineering
Primary Location : USA-California, Santa Clara
Other Locations : USA-Oregon, Hillsboro
Full/Part Time : Full Time
Job Type : Experienced
Regular/Temporary : Regular
Posting Date : Apr 25, 2013
Apply Before : Apr 26, 2014

Business Group Employees in the Intel Architecture Group (IAG) deliver innovative platforms across computing and communication segments including data centers, mobile and desktop personal computers, handhelds, embedded devices and consumer electronics. Intel's industry leading technology is used to create integrated hardware and software solutions such as processors, chipsets, communication radios, graphics processors, motherboards, and networking components that deliver capabilities from security and manageability to computing performance and energy efficiency. IAG employees are at the forefront of enabling a new era of computing that is more integrated into all aspects of our daily lives.
Posting Statement : We will accept applications/resumes until 60 days after posting date or earlier at Intel's discretion

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