The selected individual will be responsible for designing custom VLSI design circuits for high-speed processor chips in leading-edge CMOS process technology targeted at network and consumer applications. Additional responsibilities include:
Designing a complex digital block and as part of that, developing schematics, performing circuit/timing analysis, overseeing layout design work, and performing various CMOS backend-design quality checks using industry standard tools.
Working with the physical verification team in integrating custom blocks with minimal issues.
Providing technical direction, coaching, and mentoring to employees on your team and others when necessary to achieve successful project outcomes.
BS in EE with +9 years of related experience or MS +7 years of related experience.
Experience with industry standard EDA tools for schematic capture, circuit simulation, and static timing analysis is required.
Experience in designing high speed ( >2 GHz) digital circuits and understanding various design tradeoffs (performance vs power) is required.
Must have a good understanding of the following concepts: EM, IR, and DFM.
Must have a good understanding of hardware description language such as Verilog.
Experience in interfacing with RTL and Physical verification teams is required.
Strong scripting skills is a plus (PERL, TCL, UNIX shell etc.)
Must have effective interpersonal, teamwork, and communication skills.
Must demonstrate excellent analysis and problem-solving skills.
Must have an inherent sense of urgency and accountability.
Must demonstrate initiative and a bias for thoughtful action.
Must be grounded, detail-oriented, and always able to back up ideas with facts.
Must have the ability to multi-task in a fast paced environment.
Cavium, Inc. - 14 months ago