Senior Physical Architect
In this position, you will be a part of the "Switch" Silicon Engineering team located in Calabasas, CA. As a physical architect, you will be primarily responsible to ascertain that designs meet performance, area, power and scan coverage targets. You will work with RTL designers, Place & Route teams and Product Engineering teams and manage handoffs between them. To be successful in this role, you will need a deep expertise of the standard ASIC tool flow, combined with a methodical approach to implementation and problem solving. We will be particularly interested in candidates with good communication skills and a track record of technical leadership. You will work in all aspects of the ASIC design cycle, including:
- Understanding design data-flow as well as the chip-level floor-planning constraints, based on which you will set up initial floor-plans with macro/pin placements and keep-outs.
- Work with RTL designers in setting up timing constraints, clock domains and multi-cycle paths based on spec requirements.
- Interpret timing reports and work with RTL designers in solving timing problems by re-pipelining, threshold modifications, etc.
- Understand the physical effects of logic design using physical synthesis and trial P&R runs and work with P&R engineers to address placement density and routing congestion problems.
- Work with DFT engineers and RTL designers in setting up custom scan chains and addressing problems of scan compression and scan coverage.
- Writing custom scripts and defining tool flows to manipulate synthesis and physical design tools for specific applications.
- BS or MS degree in Electrical Engineering, Computer Engineering, Computer Science, or a similar field.
- 3 or more years of experience with the physical architecture life cycle (defining floor-plans & timing constraints; debugging & solving timing closure, power optimization & scan coverage problems).
- 3 or more years of experience with ASIC tools (synthesis, place & route, atpg, formal verification, timing verification).
- 3 or more years of experience with scripting languages such as Perl, TCL, Python, etc.
Additional preferred qualifications:
- Extensive experience in Synopsys tool suite (DC topo, ICC, Primetime, TetraMAX, DFTMAX).
- Extensive Design Automation experience in defining and setting up application specific tool flows.
- Static timing experience with multiple interfaces (SerDes, CDCs).
- Experience with clock domain crossing checks.
- Knowledge of multiple troubleshooting techniques for logic equivalency checks.
- Prior experience in EDA/CAD software development using object-oriented programming languages like Java or C++.
USA-California, Thousand Oaks
Jan 18, 2013
Jan 19, 2014
Employees in the Intel Architecture Group (IAG) deliver innovative platforms across computing and communication segments including data centers, mobile and desktop personal computers, handhelds, embedded devices and consumer electronics. Intel's industry leading technology is used to create integrated hardware and software solutions such as processors, chipsets, communication radios, graphics processors, motherboards, and networking components that deliver capabilities from security and manageability to computing performance and energy efficiency. IAG employees are at the forefront of enabling a new era of computing that is more integrated into all aspects of our daily lives.
We will accept applications/resumes until 60 days after posting date or earlier at Intel's discretion
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