Senior Analog Layout Design Engineer
Alliance Search Group - Westlake Village, CA

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Senior Analog Layout Design Engineer

The candidate must be able to produce high-quality IC layouts, starting from schematics, at both block level and chip level. The candidate will also plan, organize, execute, and thoroughly document his/her work, with limited supervision.


o Minimum 3 years of experience in analog, mixed-signal IC layout and mask design in CMOS technology. o Extensive experience with CAD design tools and verification flows, such as Cadence DFII and Mentor Graphics Calibre (LVS/DRC). o Experience with post layout parasitic extraction tools (example: Calibre XRC) and parasitic reduction techniques. o Experience with analog layout methodologies and techniques to maximize component matching, improve noise immunity, and optimize layout parasitics for high speed performance.
o High-level of discipline to produce high-quality documentation.

o Self-motivated, with a passion for imaging technologies. o Strong verbal communication skill. o Education: BS/MS/PhD in Electrical Engineering, Computer Engineering or Computer Science. Desirable: o Knowledge of Cadence SKILL, Verilog, and Perl languages is a plus. o CMOS design experience, and knowledge of analog circuit principals. o Experience with circuit simulators, such as HSPICE and SPECTRE. o Knowledge of hardware design and digital design flow is a plus. MISC: o Will sponsor H1B visa transfer. o Potential hiring bonus and relocation reimbursement offered Please email your resume in Word format to Ashley Hammond at


Alliance Search Group - 15 months ago - save job - copy to clipboard