IC Design and layout Engineer
ACS NATIONAL - Santa Clara, CA

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6 months+

Santa Clara, CA

IC Layout on TSMC 65nm CMOS process. Cell & transistor level layout, block and chip level integration.

Necessary Skills (Must Have):
IC layout on TSMC 65nm CMOS process. Cell & transistor level layout, block and chip level integration. Be able to run Calibre DRC/LVS standard tool.

Zack Friend
Sr. Technical Recruiter
ACS National
76 Treble Cove Rd
N. Billerica, MA 01862
Zack.Friend@acsnatl.com
800-661-8272 ex. 1107 (phone)
978-667-6190 (fax)

www.linkedin.com/in/zackfriend

Monster - 18 months ago - save job