Sr Mask Designer - 705291
Intel - Hillsboro, OR

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Sr Mask Designer - 705291 Description
      Come join Intel Labs; Intel's premier research group!

      The Integrated Platforms Research Lab (IPR), within Intel Labs, is responsible for driving flexible platform integration, SoC architecture enablers, wireless, as well as digital, analog, and physical design factors for Intel. The SoC Design & Methodology team is part of this lab.

      As a Mask Designer in IPR, you would be responsible for a variety of technical and non-repetitive tasks associated with all phases of chip development, up to and including block- and chip-level design. Responsibilities may be directed at a specific point in the design cycle, or vary as the project progresses through the design stages. Under minimal supervision typically perform as a fully proficient block or unit-level designer, capable of any unit-level layout task, or perform as a full-chip planner.

      Responsibilities may include, but are not limited to the following:
      - Utilize Intel's internal and external CAD tools, follow physical and electrical design rules and established layout methodology to complete a wide variety of highly complex assignments at the block, unit- or chip-level
      - Layout generation at the cell, block, and unit level consists of but not limited to the following: High speed CMOS circuits, PLL's, Clock and Data Recovery circuits, Filters, DAC, ADC, Low Noise Amplifiers, Switched capacitor circuits, Regulators, VCO's, Register File Arrays, as well as the physical synthesis and automatic place and route of small digital logic blocks
      - Plan, draw, assemble and verify highly complex FUBs or units. This includes block or unit floor planning and signal planning of power, clock, critical signals, and busses. Read complex verification log files and implement the appropriate layout fixes. Produce block- or unit-level database that is ready for tapeout.
      - Independently generate layout plans for complex blocks. Independently balance planning and implementation effort for maximum productivity. May guide the planning activities of junior mask designers.
      - May perform full-chip planning, assembly, or verification.
      - Provide high-level technical leadership to immediate design team. Provide layout and schedule advice, suggest design priorities, give quality feedback, answer technical questions, and role model systematic problem solving skills. Lead plot reviews, share tool knowledge, and propagate best known methods.
      - May develop and deliver training (layout tools, project methodology) to team members within the scope of the project or beyond. Provide informal training and coaching to both circuit and mask designers.
      - Assist with defining layout methodology and the evaluation and integration of new tools.
      - May contribute to engineering activities (e.g., Synthesis/APR flow, evaluation of analog layout productivity tools, build and run circuit simulations).

      The ideal candidate should exhibit behavioral traits that indicate:
      - Ability to role model effective leadership and communication skills;
      - Excellent teamwork behavior and a profession attitude that contributes to a positive project environment
      - Strong talent to consistently meet deadlines in a fast paced work environment
      - Quick adaptability to changing requirements

      You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through relevant previous job and/or research experiences.

      Minimum qualifications
      - Must have an AS/AAS or BS in ET, EET, EE, CE or CS or a minimum of 8 years of experience in a Mask Designer role without an Associates or Bachelor's degree
      - Minimum 6 years of working experience as a Mask Designer in a high technology environment
      - Minimum 6 years of experience with primary design tools (layout editors, chip planning/assembly, auto-place- and-route tools) and project macros
      - Minimum 6 years of experience with advanced UNIX skills and reading/writing basic shell scripts

      Preferred qualifications
      - 10+ years of experience in the above skill sets
      - 6+ years of experience with writing scripts (Perl, SKILL, tcl) and tool macros

      Job Category : Engineering
      Primary Location : USA-Oregon, Hillsboro

      Full/Part Time : Full Time
      Job Type : Experienced
      Regular/Temporary : Regular
      Posting Date : Feb 20, 2013
      Apply Before : Apr 21, 2013

      Business Group Intel Labs is the company's world-class, industry leading research organization, responsible for driving Intel's technology pipeline and creating new opportunities. The mission of Intel Labs is to deliver breakthrough technologies to fuel Intel's growth. This includes identifying and exploring compelling new technologies and high risk opportunities ahead of business unit investment and demonstrating first-to-market technologies and innovative new usages for computing technology. Intel Labs engages the leading thinkers in academia and industry in addition to partnering closely with Intel business units.
      Posting Statement : We will accept applications/resumes until 60 days after posting date or earlier at Intel's discretion