Staff Logic Design Engineer
Tabula - Santa Clara, CA

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Successful candidate will be working on the cutting edge 28nm technology node to develop Tabula’s next generation programmable logic solution. He/She will be involved in the design and bring-up of high performance communication and memory interfaces (e.g. SPI4/DDR4/DDR3/QDR etc). Candidate will also contribute to the definition and design of other high performance blocks on the Tabula leading edge family, and in the development of logic design infrastructure.

  • • Proficient and skilled at logic design
  • • Test and debug experience for design verification and validation
  • • Good understanding of system and signal integrity issues
  • • Experience designing with Communication and Memory protocols
  • • Proficient with scripting languages (e.g. Perl) to assist and accelerate design process

Preferred Skills:
  • • Prior experience designing high performance I/O interfaces
  • • Prior experience with PLL / DLL/ IO design or applications
  • • Familiarity with different simulators, ASIC flow, and verification tools
  • • Skills and aptitude programming and experience with large scale software development flows

Years Experience:
  • • 5+ years logic design experience

Education Requirements:
  • • BSEE required, MSEE preferred

Unique opportunity to design I/O ring for an innovative programmable logic device on the industry’s leading edge 28nm technology. Work with a strong team of seasoned veterans on designs that support a wide variety of standards, protocols, and applications

*No Agencies Please.