Component Design Engineer - 707142
Intel - Santa Clara, CA

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Component Design Engineer - 707142 Description
Job Description: In this position, you will manage and provide technical leadership working with extended teams within and outside of the team to lead the netlist to tapein phase of SoC design projects.Your responsibilities will include but not be limited to:
- Managing multi-site design projects for products and partnering with internal/external IP/flow providers to meet project goals.
- Working with internal technical teams to manage the development of implementation methodology, design collateral requirements and design flow
- Managing the implementation of APR physical design clusters, such as pre-layout synthesis/optimization, floor planning, power-grid and clock tree designs, timing budgeting, place and route, RC-extraction and integration
- Managing the verification of physical designs, such as functional equivalency, timing/performance, noise, layout rules, reliability and power
- Planning, reviewing and ensuring resources are in place for activities in engineering function to meet schedules, standards, and cost
- Identifying and analyzing problems, plans, tasks, and solutions
- Setting strategic direction and building strong technical organization
- Fostering innovation and fast TTM/derivatives.

Qualifications
BS + 9 yrs. exp.; MS + 6 yrs. exp.; PhD + 4 yrs. exp. in Electrical and/or Computer Engineering. Prior experience should include hands on experience with delivery of RTL2GDS for tape-in of projects.

Looking for a senior APR First Level Manager/lead with knowledge/skills of tools/flows and methodologies used for BE design on SOC (system-on-chip).

-Must have 7+ experience with APR using Astro/ICC, static Timing using PrimeTime and Physical Verification (DRC, DEN, NAC, LVS) of clusters and/or full chip layout using Hercules.
-Must have 7+ years of Exposure and physical implementation of ECOs related to timing, noise, RV, physical verification and functional issues.

Knowledge/expertise in tools used for macro/EBB integration and layout design is highly recommended. Candidate should have strong UNIX/scripting skills.

Knowledge of advanced sub-micron processes (32nM and lower), DRC rule sets, design kit cells/usage, etc. would be required.

Project planning and coordination within the BE team, management, logic and HIP circuit designers and Fab/Package Designers required.

Management experience desirable.
Knowledge of CPU and chip set architectures would be an added advantage.

Job Category : Engineering
Primary Location : USA-California, Santa Clara

Full/Part Time : Full Time
Job Type : Experienced
Regular/Temporary : Regular
Posting Date : Mar 12, 2013
Apply Before : Mar 13, 2014

Business Group Employees in the Intel Architecture Group (IAG) deliver innovative platforms across computing and communication segments including data centers, mobile and desktop personal computers, handhelds, embedded devices and consumer electronics. Intel's industry leading technology is used to create integrated hardware and software solutions such as processors, chipsets, communication radios, graphics processors, motherboards, and networking components that deliver capabilities from security and manageability to computing performance and energy efficiency. IAG employees are at the forefront of enabling a new era of computing that is more integrated into all aspects of our daily lives.
Posting Statement : We will accept applications/resumes until 60 days after posting date or earlier at Intel's discretion

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