Senior FPGA Engineer - Lead
Ciena Corporation - San Jose, CA

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Ciena Corporation, the network specialist, offers leading network infrastructure solutions, intelligent software and a comprehensive services practice. Our portfolio of software-centric optical and Ethernet platforms combines network element programmability, operating system commonality and management unification, and Carrier Ethernet-based transformation to enable our customers to change the way they compete. Our solutions form the foundation of many of the largest, most reliable and sophisticated service provider, enterprise, government, and research and education networks across the globe.

Position Summary
The Lead Logic Engineer is responsible for developing and implementing market differentiating features in FPGAs for Carrier Ethernet products. This individual will collaborate closely with board, system, and software teams to ensure that Ciena’s products provide leading edge features for the Carrier Ethernet market.
Essential Duties & Responsibilities
  • Design of FPGAs using in-house and third-party intellectual property. This includes RTL coding, simulation, implementation, and documentation
  • Work with Product Management, Field and Service engineers to derive new product features from customer requirements and industry standards
  • Define, implement, test and integrate new features into existing product lines
  • Work with Software Engineers and QA teams to integrate and prove out complete solutions
  • Work with System test directly, or with remote customer to debug complex issues
  • Select FPGAs and related system level components. Participate in board bring up and debug
Required Skills

  • Strong team player with the ability to work in collaborative groups or alone with a minimum of supervision
  • Must be able to manage multiple simultaneous tasks
  • Must be able to organize and communicate clearly
  • Must be able to quickly understand and leverage existing IP
  • Experience in team leadership and task scheduling and management
  • Proficient in digital design, RTL implementation and simulation using Verilog
  • Experience using Unix/Linux systems
  • Knowledge of standard EDA tools, including working knowledge of TCL, Perl, or similar
  • Experience using Unix/Linux systems
  • Background in Ethernet technologies
  • Experience in developing products which support IEEE 802.1, IEEE 802.3, MEF, IETF, ITU-T standards
Experience Required

  • Minimum 7 years of related experience
  • Experience in ASIC or FPGA development including documentation and development of major RTL modules and behavioral test bench
. Experience with Altera Quartus II tools and Intellectual Property
. Experience in ASIC/FPGA development processes including documentation, and development of major RTL modules and behavioral test bench
  • Must be able to develop new tests, scripts, and maintain documentation
  • LI-CN
Ciena is an equal opportunity corporation and does not discriminate on the basis of race, color, sex, national origin, religion, age, disability or veteran status in admission or access to, or treatment or employment in, its programs and activities.

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