STA Design Engineer
Apple - Santa Clara Valley, CA

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As a senior member of the SOC Design team you will be responsible for the following
  • Full chip and block level timing closure ownership throughout the entire project cycle (RTL, synthesis and physical implementation)
  • Develop and maintain methodology and flows related to timing verification and closure
  • Generation of block and full chip timing constraints
BSEE / MSEE is required

This position requires thorough knowledge of the ASIC design timing closure flow and methodology. The ideal candidate will have the following background
  • At least 5+ years experience in ASIC timing constraints generation and timing closure
  • Expertise in STA tools (Primetime) and flow
  • Knowledge of timing corners/modes, process variations and signal integrity related issues
  • Hands on experience in timing/SDC constraints generation and management
  • Proficient in scripting languages (Tcl and Perl)
  • Familiarity with synthesis, logic equivalence, DFT and backend related methodology and tools
  • Strong communication skills are a pre-requisite as the candidate will interface with a lot of different groups
  • Self starter and highly motivated

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