Design Senior Staff Engineer
MindSpeed - Newport Beach, CA

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The successful candidate will have been part of a team completing multiple "full cycle" development projects from concept through successful production release of silicon. Demonstrated proficiency in creating RTL level designs from architectural level specifications and the ability to optimize those designs to achieve desired goals for frequency, area and power consumption are critical requirements. The engineer should also be familiar with logic synthesis and static timing analysis and ideally an expert in these areas. Complete fluency in the Verilog language is a must and proficiency with one or more scripting languages is ideal.

The engineer must be able to create and track plans for their work, anticipate and mitigate risk areas and have a strong sense of commitment to quality and timely delivery of their work. Verbal and written communication must be clear. The ability to work both individually and as an effective part of a team is also essential.

Familiarity with wireless communication standards is desirable but not essential.

As a critical part of the team developing leading edge wireless communication SoCs, the Sr. Staff Design Engineer will have primary ownership for a major functional block within the chip and be responsible for all steps in the design flow from concept through production release of silicon. Major activities include creation of design specs, RTL coding and debug, optimization to meet goals for frequency, area and power consumption, logic synthesis and support of the physical timing closure activity.
Close productive interaction with counterparts in all major partner organizations is also key to success: architecture, verification, physical design, software, package, PCB test engineering.