The candidate will be primarily responsible for helping the Standard Cell Design Team with their automation task related to design, layout, validate and maintain Standard Cell Library’s and I/O Library. |
The candidate’s duties include:
· Support CAD library development including the design and characterization of Standard Cell Libraries, specialty cells, macros and I/O pads;
· Write and simulate behavioral verilog models for Standard Cells and I/O Pads;
· Perform schematic capture design using Cadence suite of tools;
· Develop and support design methodologies;
· Analyze and specify cell library requirements in support of new product development;
· Utilize specific skills in VLSI circuit design, circuit simulation and design verification, Digital Standard Cell Library Design, And Verilog Modeling to accomplish the work.
Job Requirements :
Bachelors degree or higher in computer science, or computer engineering.
Excellent oral and written communication skills.
Excellent technical writing and presentation skills.
Linux/Unix/GNU Development tools.
Scripting (TCL or Perl is serious plus)
Digital Design, EDA and Circuit Simulation experience.
Exposure to Verilog, SystemVerilog, VHDL.
Linux System Administration
Offer Relocation :