Develop DFT architecture as per project requirements & Implement it using industry standard tools and internally developed methodologies.
Work independently or as part of a team.
Own single blocks to entire chip level synthesis/DFT.
Assist customers in bringing up chips and ATE and debug failures.
Familiarity with one or more of Mentor, Synopsys, Cadence and Logicvision tools.
Implementation of JTAG, MBIST, Custom MBIST, Scan, ATPG, At-speed Scan, Scan Compression and Logic BIST.
MBIST Redundancy/Repair Implementation
Experience with Logic Synthesis, Timing Constraints and Formal Verification.
RTL coding/Verification for the Custom implementation
Knowledge of Perl, AWK scripting.
Familiarity with industry standard testers and assist in post silicon silicon bring up on ATE.
Pattern generation, Simulation and Hand-off & Strong Simulation and debug skills
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