Product Development Engineer - Cache/RF Test Dev - 711681
Intel - Massachusetts

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Product Development Engineer - Cache/RF Test Dev - 711681

As a member of our team, you will be working in the Product Development Engineering (PDE) team within Server Development and Manufacturing Group focused on development and introduction of new generations of Xeon and Itanium microprocessors.

Product Development Engineers are responsible for ensuring the testability and manufacturability of integrated circuits from the component feasibility stage through production ramp.

Following are examples of activities in which Product Development Engineers make significant contributions:
-Development and validation of design for test circuits (DFT) with focus on cache and register file testability
-Development of test programs, methods/strategies to solve complex manufacturing testability challenges;
-Development of software programs to convert design validation test cases to tester usable patterns/vectors;
-Development and debug of test algorithms and patterns for structured array testing and other special circuits;
-Integrated circuit debug and validation to guarantee component margin to spec;
-Analysis of component specification versus performance to ensure optimal match with production equipment capability with specific emphasis on yield analysis and bin split capability;
-Analysis of early customer returns with emphasis on test hole closure activities; optimization of component production relative to both quality and cost constraints.

This position will have a heavy focus on test development for microprocessor cache arrays and register files, including test program and test pattern development, pre-silicon validation and post-silicon robustness validation.

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your school work, research and/or relevant previous job and/or internship experiences.

Minimum qualifications:
Must have BS or MS in Electrical Engineering, Computer Engineering or Electrical and Computer Engineering. At the BS level only, must have the unrestricted right to work in the US without requiring sponsorship.

Minimum of MS and 1+ year, or BS and 3+ years of experience with the following skill sets:
- Experience with test methodologies, algorithms and DFT for memory/structured arrays
- Experience with pre-silicon validation and test development (logic simulation/validation using RTL)
- C, C++ and/or Perl (or equivalent scripting language)
- Working knowledge of digital and/or analog circuit design methodology
- Working knowledge of computer/microprocessor architecture
- Working knowledge of Design for Test methodologies and circuits
- Statistics and data analysis

Preferred qualifications
- 1+ years of VLSI ATE test program development
- Memory or Design for Test (DFT) circuit design experience

Job Category : Engineering
Primary Location : USA-Massachusetts

Full/Part Time : Full Time
Job Type : Experienced
Regular/Temporary : Regular
Posting Date : May 15, 2013
Apply Before : May 15, 2014

Business Group Employees in the Intel Architecture Group (IAG) deliver innovative platforms across computing and communication segments including data centers, mobile and desktop personal computers, handhelds, embedded devices and consumer electronics. Intel's industry leading technology is used to create integrated hardware and software solutions such as processors, chipsets, communication radios, graphics processors, motherboards, and networking components that deliver capabilities from security and manageability to computing performance and energy efficiency. IAG employees are at the forefront of enabling a new era of computing that is more integrated into all aspects of our daily lives.
Posting Statement : We will accept applications/resumes until 60 days after posting date or earlier at Intel's discretion

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