These contractors will fill a short-term staffing gap. They will work in the SoC Design team and enabled the completion of tasks to meet schedule.
Daily Responsibilities: Candidates will be responsible for various RTL design tasks related to SoC Design and integration.
Necessary Skills (Must Have):
MUST be a U.S. Citizen or have a Green Card
Bachelor or Masters of Science degree in Electrical Engineering
System Verilog RTL coding VCS RTL Simulator Knowledge of SoC Design incl. Design for Testability Knowledge of SoC clocking and reset Knowledge of Lint, Synopsys Synthesis
- 5 years or more of experience as a RTL design engineer to work in the Front-end RTL.
- 4 years or more years experience as a unit RTL design owner for complex IPs on large ICs/SoCs.
- 4 years or more experience in SystemVerilog or Verilog coding.
- 4 years or more experience in synthesis and timing closure.
- 2 years or more experience with SoC level low-power design methodologies, and clocking/reset.
Additional Desired Qualifications:
Knowledge of O-in Clock Domain Crossing tool Knowledge of TAP Controller, MBIST and Scan for high volume manufacturing
- Knowledge of DFT or DFx techniques (required for 1-2 position s)
- Knowledge of OVL/SVA assertions.
- Experience in high-speed serial protocols, such as Serial ATA, USB, PCI-Express, etc.
- Knowledge of coverage-driven functional verification, test plan development and test plan execution.
Synergy Seven - 16 months ago