Power Methodology Lead
Apple - Santa Clara Valley, CA

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Title: ASIC Power Methodology

Description:
The SoC hardware development team is looking for an experience engineer to lead the implementation of power architectures, power reduction techniques and power methodologies.

Core Responsibilities:
The main responsibility of this role is to drive the design implementation for very power efficient product.
  • Develop new techniques for power efficiency in our products
  • Guide design implementation to achieve the power targets.
  • Create or improve new methodologies to improve power.
  • Maintain power roll-up at the chip level
  • Understand interactions of the product at the software and system level that impact power.
Qualifications:
The candidate should have experience in low power architecture, ASIC design implementation for low power, ASIC physical design methodology.

  • Experience with low power logic implementation
  • Experience with low power architecture techniques
  • Familiarity with ASIC design flows.
  • Familiarity with physical design tools for power optimization.
  • Strong communication skills are a pre-requisite as the candidate will interface with a lot of different groups
Education: BSEE/MSEE or Computer Science required.

Education: BSEE/MSEE or Computer Science required.

Qualifications:
The candidate should have experience in low power architecture, ASIC design implementation for low power, ASIC physical design methodology.

  • Experience with low power logic implementation
  • Experience with low power architecture techniques
  • Familiarity with ASIC design flows.
  • Familiarity with physical design tools for power optimization.
  • Strong communication skills are a pre-requisite as the candidate will interface with a lot of different groups

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