Lead Physical Design Engineer
Job Description: Key responsibilities will be to mentor and lead a team in the creation of cell, block and macro level abstract, custom layout and DRC/LVS verified analog layout circuits using industry leading technologies and design tools. Perform RC extraction and EM analysis to troubleshoot difficult design issues and apply proactive intervention. Participate and lead others in developing methodologies and flow efficiencies. Troubleshoots a wide variety of issues, up to and including difficult design issues and applies proactive intervention. Schedules, staffs, executes and verifies complex chips development and execution of project methodologies and/or flow developments. Requires expansive knowledge and practical application of methodologies and physical design.
-Bachelors of Electrical Engineering with minimum 4-5 years of custom analog layout design in leading CMOS processes
-Minimum 1-2 years experience in an analog layout lead role
-Experience in high-speed custom layout
-Experience in scheduling work and tracking progress
-Proficient in floorplanning, RC extraction, layout optimization and verification
-Ability to contribute and work in a multi-site team setting
-Working knowledge of UNIX with experience in scripting and debugging
-Understanding of ESD, lithography, EM, antenna effects and manufacturing challenges (utilizing tools such as Totem, RedHawk, etc.)
-Masters of Electrical Engineering
-Excellent oral and written communication skills
Mar 27, 2013
As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to final test and optimization, and lastly packaging. Employees in the Technology and Manufacturing group are part of a worldwide network of manufacturing and assembly/test facilities.
We will accept applications/resumes until 60 days after posting date or earlier at Intel's discretion
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