The Qualcomm Processor IP Team is looking for an experienced Logic Design Engineer to join a team of designers to develop next generation Snapdragon IP for on-chip interconnects.
Duties include design, implementation, and verification support of the Interconnect IP developed.
The successful candidate will:
- Participate in unit-level micro-architecture development and design documentation
- Implement logic in Verilog RTL based on high-level specifications and team meetings
- Provide verification specifications and debug support for sub-unit functions
- Participate in unit and top-level synthesis and timing closure
The Candidate must have a Solid understanding of:
- Cache coherence state transitions for coherent SMP and coherent NUMA systems.
- Coherency protocol extensions necessary to support multi-node/multi-socket cache and IO coherency, handling of coherent and non-coherent traffic classes, and inter-node/socket interrupt delivery High speed IO interfaces (transaction, link, and physical layers) such as PCIe (Gen 2/3), Rapid IO, DDR, QPI, and HT/cHT.
- Protocol and transaction encapsulation. High frequency design & synthesis techniques, Cache Controller or CPU micro-architecture design and RAS requirements for chip interconnects.
- 3+ years of experience in ASIC/SoC, CPU, Caches and Chip Bus Interconnect
- Must have excellent system debug skills
- Experience in high speed digital design
- Knowledge of state of the art verification techniques such as constraint driven random testing
- Excellent oral and written communication skills
- Ability to work in a team environment
Required: Bachelor's in Computer Engineering, Computer Science, or Electrical Engineering with 3+ years of experience in ASIC/SoC, CPU, Caches and Chip Bus Interconnect. Master's Preferred.
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