Processor Core IP Development Lead Verification Engineer - Austin, Texas
Qualcomm 408 reviews - Austin, TX

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The Qualcomm Processor IP Team is looking for an experienced Design Verification Engineer to lead a team of engineers to verify the next generation of Snapdragon IP for on-chip interconnects. The Verification Engineer will be responsible for developing and integrating verification environment components, creating test plans from functional specifications, and writing, executing and debugging tests for the core IP.

You will be leading the verification effort of complex IP blocks. You will define core level verification strategies, test plans, and develop tools and scripts to enable testing, triage, and coverage collection in an efficient, automated fashion. You will work with the subsystem and chip teams to develop reusable verification environments for vertical integration. You will verify a core for bus certification, full functionality, high performance, and low power.

The successful candidate will:
- Drive in unit-level micro-architecture development, design and verification documentation
- Provide verification specifications and debug support for sub-unit functions
- Participate in unit and top-level design and coverage reviews
- Work with design team members across other disciplines
- Meet all quality and performance requirements

- 10+ years of experience in ASIC/SoC, CPU, Caches and Chip Bus Interconnect Verification
- Strong knowledge in Object Oriented programming, data structures, and algorithms
- Strong knowledge of HVLs(VERA/e/SystemVerilog), HDLs(Verilog/VHDL), C/C++
- Strong knowledge of coverage driven, constrained random verification and testbench architecture for vertical reuse
- Must have hands-on experience and strong knowledge on HVL methodology (UVM, OVM, VMM, RVM), testbench automation, industry standard bug tracking, and regression mechanisms.
- In-depth knowledge in SoC architecture, including CPUs (preferably ARM), memory subsystems and controllers (PCDDRx), peripherals (PCIe, SATA, Ethernet) , multi-domain clocking, and bus & interconnect structures (preferably as AHB and AXI)
- Must have excellent system debug skills
- Excellent oral and written communication skills
- Ability to Lead in a team environment

Required: Bachelor's in Computer Engineering, Computer Science, or Electrical Engineering with 10+ years of experience in ASIC/SoC, CPU, Caches and Chip Bus Interconnect Verification. Master's Preferred.

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408 reviews
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