Senior Packaging Assembly Engineer - 700935
Intel - Santa Clara, CA

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Senior Packaging Assembly Engineer




Senior Packaging Engineers provide project management, package design/development and sustaining support for optical transceiver assemblies, various other electronic components and/or completed units. This position will define overall package performance and specification and realizes technology certification through layout design and test vehicle design. Additional responsibilities will include:

  • Conducting tests and research on basic materials and properties
  • Establishing material specifications for contract assemblers and raw material vendors
  • Interfacing with Quality Assurance and Purchasing regarding material quality and vendor performance
  • Providing consultation concerning packaging problems and improvements in the packaging process
  • Responding to customer/client requests or events as they occur
  • Developing solutions to problems utilizing formal education and judgment
The ideal candidate should exhibit behavioral traits that indicate:

  • Strong verbal and written communication skills
  • Good leadership skills
  • A positive, Can-Do attitude


You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through relevant previous job and/or research experiences

Minimum qualifications

  • Must have a BS, MS or PhD in Mechanical Engineering, Industrial Engineering, Manufacturing Engineering, Material Science, Electrical Engineering or Computer Engineering
  • Minimum 5 years of experience with optoelectronics or microelectronics component industry, packaging and/or PCB assembly
  • Minimum 5 years of experience with epoxy material selection, characterization and qualification for packaging application
  • Minimum 3 years of experience with backend processes of assembly and automation (i.e., flip chip wafer bumping and assembly, wire bonding, Die bond, die saw, solder, dispensing and/or surface mount technology)
  • Minimum 3 years of experience with automation equipment and related statistical analysis software
  • Minimum 3 years of experience with D.O.E., DFMEA, PFMEA and structured new product introduction(NPI) release processes
Preferred qualifications

  • 5+ years of experience within a high volume manufacturing environment and/or collaborating with global manufacturing teams
  • 3+ years of experience with precision alignment for optical device
  • 3+ years of experience with project management
  • 3+ years of experience with Fine pitch Flip Chip
Job Category



Primary Location


USA-California, Santa Clara

Full/Part Time


Full Time

Job Type






Posting Date


Nov 13, 2012

Apply Before


Nov 14, 2013

Business Group

Intel Labs is the company's world-class, industry leading research organization, responsible for driving Intel's technology pipeline and creating new opportunities. The mission of Intel Labs is to deliver breakthrough technologies to fuel Intel's growth. This includes identifying and exploring compelling new technologies and high risk opportunities ahead of business unit investment and demonstrating first-to-market technologies and innovative new usages for computing technology. Intel Labs engages the leading thinkers in academia and industry in addition to partnering closely with Intel business units.

Posting Statement


We will accept applications/resumes until 60 days after posting date or earlier at Intel's discretion

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