We receive new positions on a regular basis
We receive new positions on a regular basis .
NOTE: Due to client policy, US Citizens and Green Card Holders ONLY may apply ( F1, EAD and H1B Visas are not accepted with this client). We do have other clients where we may place you, so please do not hesitate to check our website for all our opportunities.
ContractComponent Design Eng / 156981
Contract Location: Irvine, CA
Contract Duration: up to 18 months
Remote Position: NO
Project Description: Memory expansion chip design for use in our high end server platforms in the Datacenter.
RTL coding to implement chipset functionality per Cspec, HAS, MAS
Work closely with pre-si validation team to debug failing tests
Work closely with Physical Design team to resolve timing closure issues
Document functionality, usage models as required to support stakeholders
Solid knowledge of ASIC design flows and methodologies
Solid knowledge of ASIC verification methodology
Experience writing micro-architecture spec
Experience converting micro-architecture spec to RTL design
Solid knowledge of RTL coding for synthesis using Verilog
Solid knowledge of RTL coding for DFX
Experience with Synopsys Design Compiler
Experience with timing analysis and timing closure
Experience with gate level simulations and debug
Excellent written and verbal communication skills
Required tool knowledge:
VCS, Design Compiler (synthesis)
Verilog/System Verilog, Unix C-shell, Source Code Management
Additional skills desired, but not required:
Architecture: IA, ARM, embedded controllers
Protocols : DDR, PCIE, AMBA
Tools: Lint, FPV, Perl, Tcl
HOW TO APPLY: If you are qualified and interested, please reference the contract title AND location AND send your resume in WORD format directly to firstname.lastname@example.org I will get back to you if I feel you could be a match for this position.
Formalized Design - 19 months ago