-Validation Engineer / 2 locations / Posted 7-2
Formalized Design - Santa Clara, CA

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ContractValidation Engineer / 167316

Contract Location: Hillsboro, OR or Santa Clara, CA

Contract Duration: up to 18 months

Remote Position: NO

NOTE: Due to client policy, US Citizens and Green Card Holders ONLY may apply ( F1, EAD and H1B Visas are not accepted with this client). We do have other clients where we may place you, so please do not hesitate to check our website for all our opportunities.

Daily Responsibilities:
Development of pre-silicon validation environment and infrastructure for generation of test plan for assigned cluster

Development and implementation of testbench, regression, coverage points, and ensures the coverage goal is met

Generation and execution of tests, identify bugs in the design and work closely with architecture, micro-architecture and RTL team to resolve the bugs

Necessary Skills :
Knowledge of RTL design and verification language

Ability to work with System Verilog, Specman, OVM/UVM based verification methodology; VCS, Linux, Perl, and C/C++

Experience with BFM, testbench, checkers/trackers, and test generation and debug

Experience and understanding of Coverage driven verification methods

Additional skills desired, but not required: Work experience with DDR Memory Controller design and validation

HOW TO APPLY: If you are qualified and interested, please reference the contract title AND location AND send your resume in WORD format directly to logan@formalized.com I will get back to you if I feel you could be a match for this position.

Formalized Design - 20 months ago - save job