ASIC/SoC/FPGA Lead Design Engineer
Abraxas - Annapolis Junction, MD

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Abraxas Corporation is a trusted partner to the U.S. National Security community, supporting its worldwide mission with both service and technical related programs across a vast array of Intelligence Community (IC) organizations. Our staff brings fresh perspectives from engineering, academia, national security, and defense to collaborate on multifaceted problems.

Abraxas develops special technology and implements trusted unique technical solutions to address the global challenges faced by the National Security community today and those that it will face in the future. Abraxas employs recognized experts to resolve those challenges and skilled engineers to address the product needs working across all technology domains to ensure the delivery of the most advanced comprehensive solutions.

REQUIRED: US Citizenship. Active security clearance is highly preferred. Must be willing and able to obtain a TS/SCI w/ polygraph clearance.

Abraxas is aggressively recruiting Sr ASIC/SoC/FPGA Design Engineers to work in the Annapolis Junction, MD area. The successful candidate will provide hands-on technical design leadership and be an individual contributor on ASIC/SoC and FPGA projects. The candidate will be responsible for, and contributing to, all phases of an ASIC/SoC/FPGA development starting from creation of an architectural specification through ASIC/SoC/FPGA sign-off. The ideal candidate will possess the following experience:
  • 10+ years of experience in high speed ASIC/SoC/FPGA developments.
  • Previous experience as ASIC/SoC/FPGA design lead.
  • Experience with a wide variety of ASIC/FPGA vendor technologies.
  • Significant experience with Synopsys synthesis, static timing analysis, DFT, ASIC vendor sign-off methodologies.
  • Knowledge of embedded processor architectures.
  • Experienced in writing technical specifications
  • 5+ years of RTL (Verilog) design experience (VHDL considered) including the following:
    • Front-end design, verification and specification
    • Simulation experience required
    • System Verilog verification desired
    • OVM or VMM a plus
    • Synthesis experience required
    • Experience developing timing constraints desired
    • ASIC design experience required
    • Testability experience desired (DFT compiler/Tetramax, memory BIST)
Relevant technology experience required
  • Leading edge technology (<= 90 nanometers (nm)) desired
  • Power optimization experience (UPF/CPF flow) a plus
  • Experience desired with other point tools
  • Code coverage
  • Formal verification
  • Llinter


BSEE is required. MSEE preferred.

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