FutureWei Technologies, Inc. (dba Huawei R&D USA) is a leader in IC research and development. Many of the network processors are the engines that power Huawei's state-of-the-art optical networking; wireless networking, broadband access, data communications, and video conferencing products. The company provides enterprise network solutions, including data center, networking solutions, and cloud computing. FutureWei Technologies, Inc. also develops carrier network solutions comprising metro optical, long haul optical, optical networking, mobile network, and broadband. The company was founded in 2001 and has located its R&D Headquarters in Santa Clara, California, the heart of Silicon Valley.
The CPU micro-architecture/Design Engineer will define the micro-architecture for a CPU block within a network processor ASIC. This engineer will be responsible for the micro-architecture specification and design implementation for complex datapath and control modules for a large, high complexity and high bandwidth network processor ASIC.
- Interact with the ASIC chip architect and design team to define the micro-architecture of the CPU core block used in a network processor ASIC
- Work with the performance modeling team to define the mirco-architecture for the CPU block
- Contribute to the detailed implementation of the logic design in block level. This includes providing micro-architecture specification and design implementation as required, considering all aspects of performance, timing, power, and area in a leading edge process technology
- Interact with the verification and software teams to ensure delivery of high quality design which is efficiently usable in a complex networking architecture and it is optimized for power and performance
- Minimum of 8-10 years of proven design experience in complex network processor or microprocessor projects
- Experienced in programmable NPU and/or CPU and/or GPU
- Familiar with overall microprocessor micro-architecture and design
- Familiarity with TCP/IP networking/service packet protocols is preferred
- Experienced in Integer execution datapath and control design (no FP requirement)
- Expertise in Multi-level cache hierarchy design or multi-core/multi-thread pipelined design
- Must have strong Verilog and design experience with high speed logic
- Must be a highly organized, detail-oriented self-starter, who works well independently, as well as in a team environment
- Master’s Degree preferred
- Good verbal and written communication skills
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