1 Year Contract Assignment
Design Verification Engineer Silicon Engineering -MT1111178
Job Description: Design Verification Engineer Silicon Engineering DFX group is looking for verification Engineer for a design verification of large SOC design. The ideal candidate will have strong verification background with a desire to work on Design For Test (DFT) verification. Responsibilities: - Implement the verification environment methodology to verify functionality of DFT features at IP blocks and full-chip. - Understand design architecture specification to develop detailed test plans and write test plan documentation. - Developing checkers, irritators, stimulus and functional coverage points. - Debugging and rooting causing failures from regression, suggest possible fix to design team. - Collaborate with global multi-site teams in verification effort at full-chip level.
The ideal candidate will have 6+ years of verification experience with Masters in Electrical Engineering, Computer architecture, or Computer Science. Will accept a Bachelor's degree with 8 years of experience in lieu of a Master's degree.
Job Requirements: - Strong knowledge in Verilog and testbench development. - Strong C/C++ programming skills. - Knowledge and experience with assertions based verification, coverage and advance verification techniques. - Good understanding of logic design and architecture. - Familiar with simulation, emulation and debugging tools. - Strong Scripting languages such as Perl/tcl. - Experience with successful tape-out of large SOCs from test plan to sign-off. - Exposure to design for debug and silicon debug is a plus. - Knowledge of DFT techniques such as JTAG, Boundary Scan, IEEE1500 is Scan, Memory BIST is a plus. - Must be able to manage multiple tasks concurrently and should possess strong communication skills.
12 months
GCR Professional Services - 14 months ago
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