Design for Test (DFT) Engineer - Raleigh, NC
Qualcomm - Raleigh, NC

This job posting is no longer available on Qualcomm. Find similar jobs:Design Test Engineer jobs - Qualcomm jobs

The Qualcomm Digital ASIC Design Team is currently seeking candidates for a staff position responsible for the implementation of advanced DFT/DFD (design for test/design for debug) techniques for low power, high performance and highly integrated SoCs. The successful candidate will be directly involved with implementation of various DFT architectures to achieve high quality manufacturing tests that reduce test cost, and increase production quality. The position will involve all aspects of the DFT including methodology development, design, manufacturing testing, and debug.

Implementation of advanced DFT/DFD (design for test/design for debug) techniques for low power, high performance and highly integrated SoCs.
Work with design teams to improve low coverage designs.
Work with Test Engineers to debug/diagnose manufacturing defects.

Required Experience:
Strong fundamental knowledge of DFT/DFD techniques for high performance processors
Understanding of core-based test methodology and scan isolation
Knowledge in fault modeling Stuck-at, Transition, Path Delay, Gate-Exhaustive, IDDQ, and other advanced fault models
Knowledge in JTAG, MBIST, Scan Compression, ATPG, Fault Simulation and at-speed testing
Experience with an industry standard ATPG tools like Synopsys TetraMax, Cadence Encounter Test or Mentor Fastscan
Synopsys DFTC scan insertion or equivalent
Experience in Logic Design, VHDL, Verilog RTL, verification, and static timing analysis
Working knowledge in one or more of the following; C, C++, TCL or Perl.
Experience with industry simulation tools such as VCS, Modelsim, or others
Direct experience in silicon bring-up, debug, and validation of DFT features on ATE
Detail oriented with strong organizational, problem solving, and communication skills (both written and oral)

Desired Experience:
Experience in design and verification of the above; Test Synthesis, ATPG Pattern generation, logic simulation, etc.
Experience with formal verification tools such Verplex, Formality, etc.
Knowledge and experience of timing closure and industry tools like PrimeTime and PTSI.
Experience with other industry tools such as Vera, Spyglass, 0-in, Jasper, RedHawk, PrimePower.

Required: Bachelor's, Electrical Engineering
Preferred: Master's, Electrical Engineering or equivalent experience


About this company
350 reviews
Billions, maybe trillions of times a day… That’s how often people around the world touch something made better by Qualcomm....