Join the DVP IP design team which is responsible for the design, verification and implementation of HDMI, DisplayPort, MHL and other Digital Video interfaces within the Broadband Communication Group. DVP IPs are necessary components most Settop box and Mobile ASICs today as they address secure video applications.
As a key member of the DVP design team you will:
- Develop detailed micro architectural specification
- Design RTL in Verilog from detailed engineering specifications
- Synthesize complex high speed digital designs
- Perform static timing analysis
- Apply design for test techniques
- Perform formal verification
- Debug and resolve pre/post silicon lab failures
- Make architectural/design trade offs for balancing performance/power/area
- Interface with Place and Route and Analog Design Teams
BSEE with 12+ (or MSEE with 9+) years related experience
Candidates with more/less experience will also be considered for this opening, although with a
correspondingly different title (no new college grads)
- Proficient in RTL design/simulation in Verilog
- Knowledge/Experience in all phases of ASIC design flow
- Synthesis using Synopsys tool suite
- Timing Analysis using Synopsys Primetime tool, and timing closure.
- Formal Verification and Lint tools
- DFT concepts of Scan, BIST.
- Working knowledge of C, PERL, TCL or other scripting language a plus
- Experience in System Verilog or System C a plus
- Experience with uControllers, embedded processor a plus
- Experience with high speed serdes a plus
- Excellent communication and presentation skills
- Well organized, methodical, and detail oriented
- Must be a team player and easy to work with
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