FPGA RTL Emulation Engineer - TX
Formalized Design - Austin, TX

This job posting is no longer available on Formalized Design. Find similar jobs: Fpga Rtl Emulation Engineer jobs - Formalized Design jobs

AVAILABLE NOW : FPGA RTL Design Emulation Engineer

Location: Austin, TX

Contract Length: 12 Months

Please submit your Resume directly to logan.callanan-attebery@formalized.com

Required Skills:
5+ years of experience with processor and PC system level architectures

4+ years of experience in FPGA-based emulation including: Synopsis synthesis, script writing , and object oriented design

4+ years of experience in programming using C, C++, Python, Perl, or TCL

3+ years of experience in SoC verification with SystemVerilog or Verilog, and /or VHDL coding and simulation

3+ years of experience with pre and/or post silicon validation

Bachelors or Masters in Electrical Engineering, Computer Engineering or Computer Science

Primary Focus:
Creating FPGA emulation models from RTL designs using FPGA emulation synthesis, partitions and routing tools.

Defining and documenting RTL changes required while developing hardware and software collaterals and integrating them into the FPGA model.

Debugging the FPGA emulation model, while defining and developing new capabilities and Hardware and Software tools to enable acceleration of RTL.

Improving the FPGA emulation usability for pre-Silicon and post-Silicon functional validation as well as software development and validation.

If you are interested in learning more, we would like the opportunity to discuss this with you in greater detail.

Formalized Design, Inc. Works Directly With the Hiring Manager

Please submit your Resume directly to logan.callanan-attebery@formalized.com

How to Apply: To submit your resume for consideration please email it directly to the recruiter named in the Job Ad above – Please send your current resume in Word or PDF format.

Do Not apply online – send your resume to the recruiter.