Lead Design Engineer - Hardware Systems Verification
Cadence Design Systems - San Jose, CA

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The Lead Design Engineer will work with Chip, System and Software architects to define and design next generation Industry leading advanced Emulation and co-simulation systems. Their primary focus will be on Chip and FPGA design, responsible for designing major modules on chip or system. This person will work closely with verification engineers to ensure full functional coverage on verification. They will work with the physical design team to resolve timing/sizing/power concerns.

Position Requirements

Requirements for this position include:
  • BS/MS/PhD EE/CE

  • experience in logic design for high performance Chip and/or FPGAs

  • Proficient in Verilog and SystemVerilog

  • Knowledgeable and experienced verification discipline, UVM a plus

  • Solid understanding on chip physical design and timing closure

  • Good programming skills in C/C++/shell, Perl, Python

Company Information

Cadence is the global leader in software, hardware, and services that is driving the transformation of the electronic design automation (EDA) industry. This application-driven approach for creating, integrating, and optimizing designs helps customers realize Analog & Digital ICs , System-On-Chip devices, IP and complete systems at lower costs and with higher quality.

Cadence is an equal opportunity employer and is committed to hiring a diverse workforce.

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Cadence Design Systems - 16 months ago - save job - block
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