Mask Layout Engineer - Contractor
Xilinx - San Jose, CA

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Xilinx is seeking a contractor Mask Design Engineer. The successful candidate will work as part of a team executing projects in advanced 28nm and 20nm CMOS manufacturing processes on state-of-the-art wireline transceiver layout. Project tasks will include: floor-planning; power grid and signal flowplanning; advanced transistor level layout; physical and electrical verification.

Job Requirements

* Strong foundation in layout design for analog/mixed-signal circuits in advanced CMOS processes.

* Extensive floorplanning, power grid and signal flow planning experience.

* Excellent understanding of signal and clock shielding and isolation techniques.

* Excellent understanding of process non-idealities such as STI stress, well proximity effect and design strategies to mitigate these effects.

* Experience in the layout of high-speed transceivers, PLLs, receivers, and transmitters

* Excellent written and oral communication skills are also required

* Minimum education level/experience: Diploma + 10 yrs, BS + 8 yrs

Additional Details

Xilinx Inc. is an Equal Employment Opportunity, Affirmative Action Employer that complies with all US federal and state laws regarding non-discrimination. THIS IS A TEMPORARY JOB VACANCY

Currency

USD

* Vacancy Type

Temporary

Xilinx - 20 months ago - save job - block
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Xilinx is programmed to give you control. The company is a top supplier of field-programmable gate arrays (FPGAs) and complex programmable...