Should have experience in the following:
Floor Planning, Place & Route , CTS , Physical Verification (all Cadence or Synopsys flow) STA with Synopsys tools Should have worked atleast 2 projects on SoC / Chip level Floor Planning/ PnR Post layout timing closure Should have worked on ECOs
For more clarity and information, please contact the Hiring Prime for these requirements.
Hiring Prime: Brijendra Rao
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