Principal Engineer-EFA
GLOBALFOUNDRIES - Malta, NY

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Company: GLOBALFOUNDRIES U.S., Inc.

Location: Malta, NY

Position Title: Principal Engineer-Electrical Failure Analysis

Hours: Monday-Friday, 8:00 am-5:00 pm

Summary of Duties: Provide technical leadership in using electrical and physical fault isolation techniques to identify and solve yield and reliability issues. Utilize experience with photon emission, laser injection systems, obirch; tiva techniques; utilize experience with microprobing devices with parametric analyzer; experience performing bitmap failure analysis using a focused ion beam system; utilize experience delayering and inspecting circuits layer by layer. Interpret memory design information and logical bitmap data results to fine physical location within die.

Qualifications: Requires a Bachelor’s degree in Electronics Engineering, Electrical Engineering, Circuit Design, or related engineering discipline plus 9 years of experience in the position offered or in semiconductor failure analysis engineering or Semiconductor process engineering experience. Will alternatively accept a Master’s degree in the fields listed above plus 6 years of experience or a Ph.D. in the listed fields and 4 years of experience in lieu of a Bachelor’s degree and 9 years of experience. The position requires demonstrated knowledge of semiconductor circuits and devices; knowledge of semiconductor processing and process integration; and demonstrated ability to work effectively within a global-matrixed team or environment. Proven project management, peer leadership, and mentoring skills. Fundamental understanding of circuit design and test, solid state device physics, submicron FET architectures, and the implications of electrical characteristics and performance on yield and product behavior. Experience with photon emission, laser injection systems; obirch; tiva techniques; experience with microprobing devices with parametric analyzer; experience performing bitmap failure analysis using a focused ion beam; system experience delayering and inspecting circuits layer by layer; experience interpreting memory design information; and logical bitmap data results to fine physical location within die.

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