SRAM Device Technologist
GLOBALFOUNDRIES - Malta, NY

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An SRAM Device engineer will be responsible for working on high density SRAM memory in state-of-the-art CMOS logic process technologies including 20nm high-k/MG and beyond. In this position, you will both develop and integrate high density SRAM devices into the current Logic process flows, optimized for performance, reliability, device mismatch, yield and ease of manufacturing.

You will be responsible for all aspects of the SRAM module development. This includes the structural development of SRAM bit cells, SRAM device development, integration into baseline processes, characterization of the cells, and analysis of parametric data bridging into yield engineering activity.

Position Overview

This position involves activities associated with the development and transfer to manufacturing of both high-performance and low-power CMOS technologies. Basic device concepts are received from Research and are tested and integrated into full technology solutions to satisfy the needs of our foundry customers, working closely with internal manufacturing facilities.

The role requires interaction with
  • Device modeling group and process-integration groups to determine adequate electrical and layout design rules. Based on technology definition to meet customer requirements, with the help of the modeling group, you will define electrical & process parametric targets for SRAM device spice models.
  • Test and Characterization group to analyze and debug device related issues during process development. Your work will involve the use of JMP, and other software that enables statistical analysis of large parametric and reliability data sets.
  • Layout and parametric groups to design and layout test structures (macros), working on setting up parametric programs. You will interface with process engineers (or Integration Engineers) to define and analyze appropriate process/device DOE (Design of Experiment). You will also routinely work directly with engineers in process Integration, starting with reliability issues ultimately leading to new process qualifications and improved reliability.

Specific Responsibilities
  • Successful candidates will design, execute, and analyze experiments aimed at the creation and optimization of leading-edge silicon transistor technology (20nm technology generation and beyond) within a development environment. This will include both physical and electrical data analysis, as well as extensive coordination with the joint technology development alliance integration, device, and unit process module groups.
    • SRAM cell device design and performance optimization across different cells
    • Mismatch(Avt) improvement plan and execution to meet technology Vmin requirement for low leakage and performance SRAM cell families at a given technology
    • Seamless interface role between unit process module, integration and logic device team in terms of SRAM device maturity learning during technology development
    • Standby leakage management skills by specific device leakage control engineering by taking all aspects with trade-offs into account
    • Silicon HW learning planning and execution as well as electrical data analysis
    • SRAM device targeting to meet technology requirement and working closely with modeling groups to ensure high quality spice model development
  • In addition to the achievement of industry-leading device characteristics, variability (mismatch) and reliability must be monitored and controlled to ensure manufacturability.
  • Interaction with customer design groups will also be a facet of this position in order to define technology requirements and parametric goals for GF's technology roadmaps.

Required Qualifications
  • A minimum of 5-7 years of experience in semiconductor device engineering after Master and/or Ph.D study
  • SRAM process integration knowledge and device module development experience, or related experience with a similar skill set.
  • A thorough knowledge of SRAM functional operation, CMOS device physics, state-of-the-art CMOS logic process technologies, and logic process integration is preferred.
  • Ability to aggressively execute complex process/device experiments and focus on solving problems individually or as part of a team is desirable.
  • In addition to technical proficiency, all candidates must have proven project management skills, peer leadership skills, and be able to mentor more junior engineers.
  • Strong fundamental understanding of solid state device physics, sub-0.1-micron FET architectures, and the implications of device characteristics and performance on technology and product behavior.
  • Fundamental understanding of unit process and module interactions (including all FEoL unit processes, such as shallow trench formation, fill and CMP, gate dielectric and electrode formation, implant and implant masking and activation, and gate spacer and silicide contact formation) on electrical parametric, product yield, and performance behavior.

Preferred Qualifications
  • Direct experience in low-leakage / low-power device design and optimization is strongly desired, and additional technical experience in FEOL reliability, defect inspection and reduction, yield analysis, and/or test structure design is a plus.
  • Experience with scribe test structure layout( testing macros), parametric program setup, and bench measurements and familiarity of electrical characterization is a plus.

GLOBALFOUNDRIES is the world's first full-service semiconductor foundry with a truly global manufacturing and technology footprint. Launched in March 2009 through a partnership between AMD [NYSE: AMD] and the Advanced Technology Investment Company (ATIC), GLOBALFOUNDRIES provides a unique combination of advanced technology, manufacturing excellence and global operations. With the integration of Chartered in January 2010, GLOBALFOUNDRIES significantly expanded its capacity and ability to provide best-in-class foundry services from mainstream to the leading edge.

GLOBALFOUNDRIES is headquartered in Silicon Valley with manufacturing operations in Singapore, Dresden, and a new leading-edge fab under construction in Saratoga County, New York. These sites are supported by a global network of R&D, design enablement, and customer support in Singapore, China, Taiwan, Japan, the United States, Germany, and the United Kingdom.

For more information on GLOBALFOUNDRIES, visit www.globalfoundries.com .

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