Synthesis, Static Timing Analysis, Timing Closure, and Equivalency checking
STA at CHIP/ SoC Level
Should be comfortable writing scripts in TCL and Perl to achieve higher performance and productivity through automation Work very closely with logic designers and physical design engineers (all members of the same group) to build complex SOC's Extensive timing analysis experience using PrimeTime Experience generating timing constraints from scratch for block and top levels Formal equivalency checking using LEC or Formality Low power design methodology
For more clarity and information, please contact the Hiring Prime for these requirements.
Hiring Prime: Brijendra Rao
Voice: +91 80 6694 3940
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Sasken is a leading provider of telecommunications software services and solutions to mobile terminal equipment manufacturers network...