Verification Engineer (Specman, System Verilog, OVM, ASIC/SOC)
Sasken Communication Technologies Limited - Allentown, PA

This job posting is no longer available on Sasken Communication Technologies Limited. Find similar jobs: Verification Engineer jobs - Sasken Communication Technologies jobs

Job Description

Requirements: Expertise in Building scalable HVL based verification environment for processor based SoC from Scratch using System Verilog Good experience in System Verilog OVM based verification environment development Sound understanding of Random and constrained random-verification concepts Experience with assertion based verification would be a plus

Job Description:
Driving the verification environment architecture Creating test scenarios (System Verilog OVM) Review and ensure that expected Code and functional coverage metrics are achieved

Desired Skills & Experience Verification experience in Specman or SV-OVM Experience in development of Verification environment / TB Working experience with ARM based processor for Image processing Must have work from Spec to Implemetation Must have worked through all the phases of verification including coverage and GLS
Feel to reach out at the contact below either through a call or email to discuss about the opportunity relating to your expertise.

Contact/Hiring Prime: Brijendra Rao
Contact Number: +91 80 6694 3940 (India)
Email ID:
Connect with me on LinkedIn:
Sasken Career page:
Sasken Facebook page:
Sasken Website:
Sasken Communication Technologies Limited



Additional Information

All your information will be kept confidential according to EEO guidelines.

Sasken Communication Technologies Limited - 22 months ago - save job
About this company
2 reviews